Counter

module lab1(clock,reset,funcselect,functout);//top model

input clock,reset,funcselect;
output functout;
wire [2:0]c;

countera second(.nreset(reset),.counter(c),.clk(clock));

anxor first(.in0(c[0]),.in1(c[2]),.sel(funcselect),.labout(functout));



endmodule

module anxor(in0,in1,sel,labout);

input in0,in1,sel;
output labout;

assign labout=(sel==1'b0)?(in0&in1):(in0^in1);


endmodule

module countera(nreset,counter,clk);
output reg [2:0] counter;

input clk,nreset;

always @(posedge clk or negedge nreset)
begin
if(nreset==1'b0)// when reset is 0 than all the output of counter
//will be  zero
counter[2:0]<=3'b0;
else
counter[2:0]<=counter[2:0]+3'b1;// if Reset is not zero
//than inrease the output of data by 1
end

endmodule